Semiconductor memory elements are classified into two fields, that is, a volatile memory and nonvolatile memory, and both the memories require continuous power supply in order to hold data. A flash memory as a typical example of the nonvolatile memory requires no electric power to hold data. For this reason, flash memory is most frequently used as nonvolatile memory. As micropatterning of flash memory advances, however, recently a nonvolatile memory technique including more advanced micropatterning, speed, and reliability has been proposed instead of the flash memory.
A phase-change memory element as one next-generation technique is an electrically driven, low-power-consumption memory element capable of direct overwrite and rapid switching. Rapid switching between set and reset as two resistance value states of the phase-change memory element is caused by a large electrical characteristic change between the crystal phase and amorphous phase of a phase-change recording material. An example of the phase-change recording material is a chalcogenide material layer that largely changes the voltage by a phase change. The resistance states of these two phases have 102 or more resistance changes for 1012 times of write, and the write count durability of the phase-change memory element, that is, the write count durability of the flash memory, is larger than 105. In addition, since low power consumption, low voltage driving, and a logic circuit are achieved at the same time, the phase-change memory element is well suited for the field of mobile techniques. An example of most general materials of the chalcogenide material layer of the phase-change memory element is Ge2Sb2Te5 (to be referred to as “GST” hereinafter). The basic concepts of electrically programmable phase-change memory element techniques are disclosed in, for example, patent references 3 and 4.
The structure and operation of the phase-change memory element will be explained below with reference to FIGS. 5 to 9. FIGS. 5 and 6 are exemplary sectional views respectively showing the structures of the conventional phase-change memory element in the crystal phase and amorphous phase.
FIG. 7 is a view showing the relationship between the electrical pulse time and the temperature when crystallizing and amorphizing the phase-change memory element.
FIG. 8 is an exemplary view showing the crystal structure of the chalcogenide material layer in the crystal state. A phase-change memory cell has one selector (selection transistor) and one phase-change memory element (including a chalcogenide material layer). As shown in FIG. 5, a chalcogenide material layer 707 is sandwiched between an upper electrode 708 and plug 705. The plug 705 extends through a lower insulating layer 704, and electrically connects the chalcogenide material layer 707 and a selection transistor 703. Data is written in the phase-change memory element by Joule heat generated by heating the chalcogenide material layer 707 to a temperature greater than or equal to the melting point.
After that, as shown in FIG. 6, the melted metal is rapidly cooled, and this amorphizes a portion 706, which covers the plug 705, of the chalcogenide material layer 707. This is the transition from set to reset. The opposite transition is achieved by an electrical pulse applied at a lower temperature for a longer time. Joule heat generated by this electrical pulse heats the chalcogenide material layer 707 to a temperature lower than the melting point and much higher than the temperature required for the amorphous-crystallization transition for a few hundred nanoseconds. FIG. 7 is a view showing the set-reset transition described above by the relationship between the time and temperature. Note that the chalcogenide material layer 707 in the crystal phase takes two structures, that is, a stable hexagonal structure and metastable rock salt (NaCl) structure.
As shown in FIG. 8, it is recently reported that the chalcogenide material layer 707 is almost the same as a metastable body-centered-cubic structure in the amorphous phase. This means that an interatomic bond is weak in the chalcogenide material layer 707 in the amorphous phase. Although the interatomic bond is weak, the covalent bond is not broken, and an atom has definitely not moved from its position in the lattice. A face-centered-cubic structure of Te and a local structure around Sb are partially maintained, and this leads to rapid reliable recovery to the crystal phase. In the set-reset transition as described above, the chalcogenide material layer 707 in the crystal phase is presumably a metastable rock salt structure obtained by rapid crystallization of the metastable state.
A read operation of the phase-change memory element is performed as follows.
When the selection transistor 703 is turned on, a source 701b to drain 701a path is energized, and an electric current flows through the chalcogenide material layer 707 from the drain 701a. The magnitude of this electric current changes in accordance with the difference between the electrical resistance values of the crystal phase and amorphous phase of the chalcogenide material layer. By using this difference between the electrical resistance values, a value stored in the phase-change memory element can be read out as “0” or “1”. The phase-change memory element having the structure as described above has the following problems, and various countermeasures have been made in recent years.
First, adhesion between the lower insulating layer 704 and chalcogenide material layer 707 is weak. In the phase-change memory element as described above, a thermal stress is applied by Joule heat during the transition between the crystal phase and amorphous phase. In this state, weak adhesion between the lower insulating layer 704 and chalcogenide material layer 707 is a serious problem. To solve this problem, a method by which an adhesion promoting layer 711 for reinforcing and promoting adhesion between the lower insulating layer 704 and chalcogenide material layer 707 is inserted below the chalcogenide material layer 707 as shown in FIG. 9 has been proposed. The disclosed adhesion promoting layer 711 is made of Ti-rich TiN (patent reference 8).
Amorphization is promoted, however, because a very low electrical resistivity of about 2.5×10−7 Ωm of TiN heats the chalcogenide material layer 707. As shown in FIG. 9, a portion 906 amorphized in the reset transition spreads over the entire surface of the chalcogenide material layer 707 in contact with the adhesion promoting layer 711. Accordingly, high electric power is required for the set-reset transition when compared to the case in which the portion 706 of the chalcogenide material layer 707 is amorphized as in the conventional structure shown in FIG. 6.
To solve the problems of power consumption and adhesion, the adhesion promoting layer 711 selected from TiOx, ZrOx, HfOx, TaOx, NbOx, CrOx, WOx, and Alx has been proposed (patent reference 1).
Non-patent reference 3 has disclosed that Ta2O5 used as the adhesion promoting layer 711 of the phase-change memory element functions not only as the adhesion promoting layer but also as a thermal diffusion preventing layer for preventing heat energy lost from the chalcogenide material layer 707 via the plug 705 to be described next.
Unfortunately, the technique disclosed therein adopts the tunnel current method in which an electric current passes through a wide-gap insulating layer, and hence must control the very thin insulating layer and high electrical resistivity. This poses a new problem of the difficulty in manufacturing technique.
Also, another problem concerning heat diffusion (thermal energy diffusion) that occurs from the chalcogenide material layer 707 via the plug 705 arises. The material of the plug 705 is, for example, a refractory metal such as tungsten having a low electrical resistivity. However, a high thermal conductivity as the original property of a metal having a low electrical resistivity causes heat diffusion during the set-reset transition. In particular, thermal energy lost from the chalcogenide material layer 707 via the plug 705 during amorphization (the reset transition) requires a large electric current. To solve this problem, TiOxNy, TiSixNy, TiAlxNy, TiOxNy, TaAlxNy, TaSixNy, and TaOxNy have been proposed as the adhesion promoting layer 711 (patent reference 5). However, the thermal conductivity is still as high as 0.1 W/cmK. That is, the problem that the thermal conductivity is higher than that of the chalcogenide material layer 707 or lower insulating layer 704 of the phase-change memory element remains unsolved.    Patent reference 1: Japanese Patent Laid-Open No. 2006-352082    Patent reference 2: Japanese Patent Laid-Open No. 2003-174144    Patent reference 3: U.S. Pat. No. 3,271,591    Patent reference 4: U.S. Pat. No. 3,530,441    Patent reference 5: U.S. Pat. No. 7,023,008    Patent reference 6: U.S. Pre-Grant Publication No. 2006/0113573    Patent reference 7: U.S. Pre-Grant Publication No. 2004/0195613    Patent reference 8: U.S. Pre-Grant Publication No. 2004/0026731    Non-patent reference 1: Wakiya et al., Thin Solid Films, vol. 410, pp 114, 2002    Non-patent reference 2: Yang et al., Applied Phisics Letters, vol. 66, pp 2643, 1995    Non-patent reference 3: Technical Report of IEICESDM, vol. 106, no. 593, pp 1-6